There are a number of ways to dope semiconductor wafers and form diffused junctions. One method is to use ion implantation. This method has the disadvantage that the ion implantation causes lattice damage which must be annealed out with minimum dopant redistribution in a subsequent process step. Another method uses dopant-containing gaseous sources such as B.sub.2 H.sub.6, AsH.sub.4, PH.sub.3, or POCl.sub.3 for pre-deposition of a doped layer on the wafer surface followed by a high-temperature drive-in step. Such gaseous dopants are, in general, toxic and corrosive. Attendant complex hardware, such as valves and regulators, is required. Control of gas flow patterns is needed for uniformity across the wafer and throughout a large batch of wafers. Another method entails the use of solid planar diffusion sources interleaved between wafers in a diffusion furnace. A diffusion furnace is not a cost-effective producer of single wafers and cannot be used to anneal wafers on the time scale of 1 to 100 seconds needed for ultra-shallow VLSI junctions. Large wafers (200 mm) are difficult to process at high temperature in diffusion furnaces without plastic deformation and slip. Another method uses an overlying polysilicon layer (implanted or otherwise doped) on single crystal silicon, the polysilicon acting as a dopant source for subsequent drive-in in a subsequent step. This method involves several steps. Also, it is difficult to selectively remove the polysilicon from the crystalline silicon substrate should this be desired. The presence of a thin oxide at the polysilicon/crystalline-silicon interface can dramatically affect reproducible transport of dopant into the silicon substrate. Thus, the many methods of doping in wide practice involve multi-step methods, less than optimal results, dangerous materials or complicated apparatus.